1. Field of the Invention
The present invention relates to a semiconductor integrated circuit, and more particularly to a semiconductor integrated circuit in which delay due to a parasitic capacitance between wiring lines can be reduced.
2. Description of the Related Art
In a conventional semiconductor integrated circuit, various signal wiring lines such as aluminum wiring lines are used to connect between circuit blocks of the semiconductor integrated circuit. The signal wiring lines are always accompanied by parasitic capacities. If the parasitic capacitance is large, the activation speed of the signal wiring line is delayed so that the circuit operation speed becomes slow, or late. As a result, the circuit characteristic of the semiconductor integrated circuit is degraded.
Also, in order to prevent the delay of the circuit operation speed, it is necessary to make an output transistor of a drive circuit sufficiently large such that the parasitic capacitance can be driven sufficiently. As a result, this causes the increase of a chip size and the decrease of a production yield.
The delay due to a parasitic capacitance in the conventional semiconductor integrated circuit will be described with reference to FIG. 1. In FIG. 1, the semiconductor integrated circuit is composed of the buffer circuits B1 to B5 and signal wiring lines F1 to F5. The signal wiring lines F1 to F5 are arranged in parallel adjacently to each other. The signal wiring lines F1 to F5 have wiring line resistances R1 to R5, interline capacitances Cs12 to Cs45 between the signal wiring lines and interlayer capacitances Cdf1 to Cdf5 between the signal wiring lines and a semiconductor substrate or the ground, respectively. The buffer circuits B1 to B5 drive loads (not shown), the wiring line resistances R1 to R5, the interline capacitances Cs12 to Cs45 and the interlayer capacitances Cdf1 to Cdf5 in response to input signals IN1 to IN5, respectively.
Each interline capacitance Cs12 to Cs45 is a capacitance between adjacent wiring lines F1 to F5. Accordingly, the interline capacitance becomes larger as the space between adjacent wiring lines F1 to F5 becomes narrow.
Also, the interlayer capacitances Cdf1 to Cdf5 are capacitance between the respective signal wiring line F1 to F5 and lower wiring lines or a semiconductor substrate. The input signals IN1 to IN5 to the buffer circuit B1 to B5 are similar to decoded signals and only one of the input signals IN1 to IN5 is activated. For example, when the signal IN2 is a "H (high)" level, the signals IN1, IN3, IN4, IN5 are set to "L (low)" level. Therefore, when the signal IN2 of the signals IN1 to IN5 is set to the "H" level, only the signal wiring line F2 is set to the "H" level. All the remaining signal wiring lines F1, F3, F4 and F5 are set to "L" level.
That is, the semiconductor integrated circuit is in the output state 1 in which only the signal wiring line F2 is selected. Next, when the signal IN4 is set to "H" level in the output state 1, only the signal wiring line F4 is set to the "H" level. All the remaining signal wiring lines F1, F2, F3 and F5 are set to "L" level. That is, the semiconductor integrated circuit is set to the output state 2 in which only the signal wiring line F4 is selected.
The following table 1 shows a relation of the respective signals and the output states.
TABLE 1 signal wiring line output state 1 output state 2 F1 L L F2 H L F3 L L F4 L H F5 L L
As seen from the table 1, when the state of the semiconductor integrated circuit is switched from the output state 1 into the output state 2, the signal wiring line F4 is activated from the "L" level to the "H" level. At this time, the signal wiring line F2 is switched from the "H" level to the "L" level. However, the signal wiring lines F3 and F5 arranged adjacently are fixed to the "L" level. Therefore, the activation speed decreases due to the interline capacitances Cs34 and Cs45, when the signal wiring line F4 is switched from the inactive state into the active state.
The activation speed of the signal wiring line F4 is expressed by the following equation (1) using a time constant .tau.1. EQU .tau.1=R4.times.(Cs34+Cs45+Cdf4) (1)
As seen from the equation (1), as the interline capacitances Cs34 and Cs45 increase, the activation speed becomes slow.
Next, a second conventional example will be described with reference to FIG. 2. In FIG. 2, the second conventional example is different from the first conventional example in that each of shield wiring lines G1 to G4 is arranged between corresponding adjacent two of the signal wiring lines F1 to F5 shown in FIG. 1. These shield wiring lines G1 to G4 are all fixed to the ground potential GND.
Now, when the state is switched from the output state 1 to the output state 2 as show in the above table 1, the shield wiring lines G3 and G4 function to decrease the influence of coupling noise, which is generated when the signal wiring line F4 is switched from the "L" level to the "H" level, to the signal wiring lines F3 and F5.
However, the shield wiring lines G3 and G4 are fixed to the "L" level. When the signal wiring line F4 is switched from the "L" level to the "H" level, the activation speed decreases more than the influence of the interline capacitances CG34 and CG44. In this case, the activation speed of the signal wiring line F4 can be expressed by the following equation (2) using a time constant .tau.2. EQU .tau.2=R4.times.(CG34+CG44+Cdf4) (2)
As seen from the equation (2), it could be understood that the activation speed becomes slow as the interline capacitances CG34 and CG44 increase.
Next, a third conventional example will be described with reference to FIG. 3. In the above second conventional example, the shield wiring lines G1 to G4 are fixed to the GND potential. However, in the third embodiment, the shield wiring lines V1 to V4 are fixed to the power supply voltage Vcc. In this case, the shield wiring lines V3 and V4 also function to decrease the influence of coupling noise, which is generated when the signal wiring line F4 is switched in potential, to the signal wiring lines F3 and F5. However, the activation speed of the signal wiring line F4 decreases because of the influence of the interline capacitances CV34 and CV44, as in the second conventional example.
Next, the interline capacitance between wiring lines and the structure of the semiconductor integrated circuit will be described with reference to FIG. 4. FIG. 4 is a schematic cross sectional view of the semiconductor integrated circuit composed of an insulating film 2 which is formed on a semiconductor substrate 1 and the signal wiring lines F3 to F5 provided in the insulating film 2.
In FIG. 4, the signal wiring lines F3 to F5 are composed of metal wiring lines such as aluminum wiring lines. Each of the signal wiring lines F3 to F5 is electrically separated from the other wiring lines and the semiconductor substrate 1 by the insulating film 2 formed on the semiconductor substrate 1. Also, a wiring line interval S between every adjacent two of the signal wiring lines F3 to F5 is necessary to be made as narrow as possible for high chip integration levels. For this reason, the signal wiring lines F3 to F5 are generally arranged to have the wiring line interval S equal to or narrower than the wiring line layer interval d from the main surface of the semiconductor substrate 1 to the signal wiring line F3 to F5. Thus, the wiring line interval S is made narrower with the forming process of fine patterns. Therefore, the interline capacitances Cs34 and Cs45 between the wiring lines are made relatively large. There is a case that the interline capacitances Cs34 and Cs45 are approximately 3 times of the capacitance of interlayer capacitance Cdf4 between the signal wiring line F4 and the semiconductor substrate 1.
The typical values of the interline capacitances Cs34 and Cs45 and the interlayer capacitances Cdf3, Cdf4 and Cdf5 are as follows: Cs34 and Cs45=0.33 pF, Cdf3, Cdf4 and Cdf5=0.75 pF.
In the above-mentioned first conventional example, a plurality of signal wiring lines are arranged in parallel. In this case, the activation speed when one of the signal wiring lines is activated greatly depends on the interline capacitances between the other adjacent signal wiring lines. In the first conventional example, when a selected one of the signal wiring lines is activated, a potential difference is necessarily generated between the selected signal wiring line and another adjacent signal wiring line. Therefore, it is difficult to reduce the interline capacitance.
Also, the wiring line interval is made extremely narrow with the development of the forming process of fine patterns, so that the interline capacitance becomes large. Therefore, the influence of the delay due to the interline capacitance has become a serious problem.
Also, in the second and third conventional examples, the potentials of the shield wiring lines are fixed. Accordingly, the potential differences are generated between the signal wiring line and each of the shield wiring lines which are arranged on both sides of the signal wiring line. For this reason, it is difficult to reduce the interline capacitance. Therefore, there is a problem in that the activation speed of the signal wiring line decreases due to the interline capacitance between the signal wiring line and each of the shield wiring line.
A precharge clock signal generating circuit is described in Japanese laid Open Patent Application (JP-A-Showa 63-78394). In this reference, a precharge clock pulse for precharging a memory is generated based on a system clock pulse and a delayed system clock pulse obtained by delaying the system clock pulse by a delay circuit 2. In this precharge clock signal generating circuit, a reference dummy bit line (12a, 12b) is provided to have the same length as a bit line of a memory cell section and to be connected to dummy transistors (Tr1, .sup.. . . ) of the same number as the number of memory cells per a column of the memory cell section. The wiring capacitance of the reference dummy bit line and the junction capacitances of the respective dummy transistors are used as a fixed capacitance of the delay circuit 2 in the precharge clock signal generating circuit.
Also, a semiconductor circuit is described in Japanese Laid Open Patent Application (JP-A-Heisei 5-90939). In this reference, two inverters 2B and 2C having different threshold values are provided to be supplied with a voltage V.sub.A from a wiring line 3. Further, a delay circuit 5 is provided to delay the voltage V.sub.A. Switches composed of NMOS 6 and PMOS 7 and NMOS 9 and PMOS 10 are provided on the output side of the inverters 2B and 2C, respectively. The switches are switched based on the output of the delay circuit 5 and an inverted signal of the output. The delay time of the delay circuit 5 is set such that the switching is performed immediately after the outputs of the inverters 2B and 2C are both set to the high or low level.